Critical Technology

Advanced Packaging & Heterogeneous Integration

The capacity to assemble, package and integrate semiconductors at the frontier: advanced packaging, chiplet architectures and heterogeneous integration, where system performance is increasingly won. One of the capabilities of Semiconductors & Advanced Computing.

International families: 86k2015 to 2024
Leading country: Japan1.6× the next
All families: 160khome filings included
Over five years: Rising2020 to 2024 against the five before

Year by year

Patent families by country of origin and the year of the earliest filing, 2000 to 2025; 2025 is a part year, still filling in. International families are those for which protection was sought beyond one country.

Volume

International patent families in the capability, by the year of the earliest filing.

Source: Global Institute for National Capability (GINC), 2026. Underlying patents from 107 patent offices, IFI CLAIMS and Google

Share by country

Each country's share of the year's international families, in per cent: the capability's five largest countries of origin, 2015 to 2024, and the rest of the world.

Source: Global Institute for National Capability (GINC), 2026. Underlying patents from 107 patent offices, IFI CLAIMS and Google

Country leaderboard

International patent families, 2015 to 2024, by country of origin. Growth compares the latest five full years with the five before.

Ten largest

Japan

South Korea

United States

Taiwan

China

Germany

France

Singapore

Netherlands

Austria

24,716

15,416

12,420

11,991

9,796

4,692

1,343

993

899

674


1	Japan	24,716	28.8%	0.9×	37,559
2	South Korea	15,416	17.9%	1.7×	23,289
3	United States	12,420	14.4%	1.1×	20,810
4	Taiwan	11,991	13.9%	1.3×	16,245
5	China	9,796	11.4%	1.8×	47,642
6	Germany	4,692	5.5%	0.8×	6,134
7	France	1,343	1.6%	0.8×	1,557
8	Singapore	993	1.2%	2.2×	1,309
9	Netherlands	899	1.0%	1.3×	969
10	Austria	674	0.8%	1.1×	739
11	Switzerland	616	0.7%	1.8×	660
12	United Kingdom	386	0.4%	1.0×	481
13	Canada	277	0.3%	1.7×	368
14	Italy	270	0.3%	1.0×	370
15	Belgium	178	0.2%	1.0×	187
16	Finland	176	0.2%	1.3×	187
17	Cayman Islands	166	0.2%	0.2×	362
18	Sweden	145	0.2%	0.9×	157
19	Israel	110	0.1%	0.9×	152
20	Ireland	110	0.1%	1.1×	227
21	Hong Kong	52	0.1%	1.2×	85
22	Malaysia	44	0.1%	0.5×	83
23	Türkiye	39	0.0%	1.6×	55
24	Denmark	34	0.0%	2.8×	37
25	Australia	32	0.0%	1.1×	39
26	Spain	31	0.0%	0.8×	35
27	Norway	27	0.0%	0.4×	28
28	India	24	0.0%	2.4×	39
29	Saudi Arabia	17	0.0%	0.1×	23
30	Luxembourg	14	0.0%	0.4×	14
31	Russia	12	0.0%	1.0×	128
32	Poland	11	0.0%	0.8×	21
33	Czechia	7	0.0%	0.8×	12
34	Brazil	6	0.0%	0.0×	17
35	Portugal	4	0.0%	0.3×	5
36	New Zealand	3	0.0%	0.0×	3
37	South Africa	3	0.0%	2.0×	3
38	Mexico	2	0.0%	1.0×	10
39	Hungary	2	0.0%	1.0×	2
40	Liechtenstein	1	0.0%	0.0×	1

Applicants

The largest applicants by international patent families, 2015 to 2024: across the world, then within each of the five countries with the most families in Advanced Packaging & Heterogeneous Integration. Names are as held in the source and are not consolidated across subsidiaries.

Global

85,962 international families

SAMSUNG ELECTRONICS CO LTD · South Korea

TAIWAN SEMICONDUCTOR MFG CO LTD · Taiwan

SAMSUNG DISPLAY CO LTD · South Korea

INTEL CORP · United States

MITSUBISHI ELECTRIC CORP · Japan

TAIWAN SEMICONDUCTOR MFG · Taiwan

6,808

4,301

2,524

2,029

1,644

1,524

Japan

24,716 international families

MITSUBISHI ELECTRIC CORP

MURATA MANUFACTURING CO

ROHM CO LTD

FUJI ELECTRIC CO LTD

TOSHIBA KK

KIOXIA CORP

1,635

1,238

985

923

806

747

South Korea

15,416 international families

SAMSUNG ELECTRONICS CO LTD

SAMSUNG DISPLAY CO LTD

SK HYNIX INC

LG DISPLAY CO LTD

SAMSUNG ELECTRO MECH

LG ELECTRONICS INC

6,791

2,524

937

843

619

494

United States

12,420 international families

INTEL CORP

MICRON TECHNOLOGY INC

QUALCOMM INC

TEXAS INSTRUMENTS INC

APPLIED MATERIALS INC

SEMICONDUCTOR COMPONENTS IND LLC

1,999

865

695

552

523

391

Taiwan

11,991 international families

TAIWAN SEMICONDUCTOR MFG CO LTD

TAIWAN SEMICONDUCTOR MFG

NANYA TECHNOLOGY CORP

INNOLUX CORP

ADVANCED SEMICONDUCTOR ENG

SILICONWARE PRECISION INDUSTRIES CO LTD

4,289

1,520

580

579

562

496

China

9,796 international families

BOE TECHNOLOGY GROUP CO LTD

HUAWEI TECH CO LTD

CHANGXIN MEMORY TECH INC

1.0% shared · 5,751 families in both

Japan

United States

Germany

China

South Korea

138,612

87,628

76,621

49,292

40,578

Crosswalk

How Advanced Packaging & Heterogeneous Integration is matched to the patent classifications. The entries below were chosen for it; each stands for itself and everything beneath it in the scheme, 743 Cooperative entries in all. A patent family counts when any of its codes, in either scheme and at any office, falls under one of them. Codes since retired are placed under the entries that replaced them.

Entry	Title in the scheme	Why it is chosen	CPC codes	IPC codes	Documents
H10W	Generic packages, interconnections, connectors or other constructional details of devices covered by class h10	Semiconductor packages, interposers, bonding, encapsulation and thermal control	5,388	191	9,970,301
H10B80/00	Assemblies of multiple devices comprising at least one memory device covered by this subclass	Stacked and assembled memory packages	1	1	13,891
H10D80/00	Assemblies of multiple devices comprising at least one device covered by this subclass	Assemblies of multiple semiconductor devices	8	3	4,652
H10W10/00	Isolation regions in semiconductor bodies between components of integrated devices	Left out
H10W15/00	Highly-doped buried regions of integrated devices	Left out
H10W20/00	Interconnections in chips, wafers or substrates	Left out

CPC and IPC codes are the codes in use on patent documents, at any office, that fall under the entry. Documents is the larger of the two schemes' counts of documents carrying one of them. An entry with no IPC codes can be told apart only in the Cooperative scheme.

The Cooperative codes in use that count towards Advanced Packaging & Heterogeneous Integration: 5,397 codes on 9,986,564 documents. The 150 most used are listed; the full list is in the cpc-to-capability.csv download.

Code	Title	Under entry	How placed	Documents
H10W90/00	Package configurations	H10W	In the scheme	355,882
H10W90/724	Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL	H10W	In the scheme	189,483
H10W74/00	Encapsulations, e.g. protective coatings	H10W	In the scheme	186,068
H10W72/884	Die-attach connectors and bond wires	H10W	In the scheme	154,060
H10W90/734	Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL	H10W	In the scheme	144,891
H10W90/754	Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL	H10W	In the scheme	144,541
H10W90/756	Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink	H10W	In the scheme	136,963
H10W72/20	Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps	H10W	In the scheme	122,961
H10W70/60	Insulating or insulated package substrates; Interposers; Redistribution layers	H10W	In the scheme	115,705
H10W72/073	Connecting or disconnecting of die-attach connectors	H10W	In the scheme	111,963
H10W72/0198	Manufacture or treatment batch processes	H10W	In the scheme	111,486
H10W90/701	Package configurations characterised by the relative positions of pads or connectors relative to package parts	H10W	In the scheme	98,873
H10W70/65	Shapes or dispositions of interconnections	H10W	In the scheme	96,955
H10W74/15	Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills	H10W	In the scheme	93,621
H10W72/90	Bond pads, in general	H10W	In the scheme	88,872
H10W72/00	Interconnections or connectors in packages	H10W	In the scheme	86,925
H10W72/952	Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu	H10W	In the scheme	82,020
H10W90/722	Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips	H10W	In the scheme	78,907
H10W72/5522	Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]	H10W	In the scheme	78,559
H10W72/252	Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu	H10W	In the scheme	77,560
H10W72/075	Connecting or disconnecting of bond wires	H10W	In the scheme	76,502
H10W90/736	Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink	H10W	In the scheme	75,285
H10W70/611	Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together	H10W	In the scheme	75,046
H10W72/072	Connecting or disconnecting of bump connectors	H10W	In the scheme	71,879
H10W70/635	Through-vias	H10W	In the scheme	70,909
H10W70/685	Shapes or dispositions thereof comprising multiple insulating layers	H10W	In the scheme	67,707
H10W72/5363	Shapes of wire connectors the connected ends being wedge-shaped	H10W	In the scheme	67,243
H10W72/29	Bond pads specially adapted therefor	H10W	In the scheme	64,224
H10W72/536	Shapes of wire connectors the connected ends being ball-shaped	H10W	In the scheme	63,072
H10W72/30	Die-attach connectors	H10W	In the scheme	60,974
H10W72/241	Dispositions, e.g. layouts	H10W	In the scheme	59,153
H10W72/923	Bond pads having multiple stacked layers	H10W	In the scheme	59,131
H10W74/01	Manufacture or treatment	H10W	In the scheme	57,397
H10W70/099	Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers	H10W	In the scheme	56,213
H10W74/117	Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection	H10W	In the scheme	56,013
H10W99/00	Subject matter not provided for in other groups of this subclass	H10W	In the scheme	54,669
H10W72/50	Bond wires	H10W	In the scheme	53,198
H10W72/59	Bond pads specially adapted therefor	H10W	In the scheme	52,607
H10W90/732	Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips	H10W	In the scheme	51,798
H10W72/9415	Dispositions of bond pads relative to the surface, e.g. recessed, protruding	H10W	In the scheme	51,721
H10W70/05	Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers	H10W	In the scheme	50,984
H10W72/354	Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers	H10W	In the scheme	50,841
H10W72/932	Plan-view shape, i.e. in top view	H10W	In the scheme	49,968
H10W74/111	Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed	H10W	In the scheme	49,508
H10W72/352	Materials of die-attach connectors comprising metals or metalloids, e.g. solders	H10W	In the scheme	47,752
H10W72/07236	Soldering or alloying	H10W	In the scheme	45,104
H10W40/22	Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections	H10W	In the scheme	44,729
H10W72/07251	Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting	H10W	In the scheme	42,713
H10W72/012	Manufacture or treatment of bump connectors, dummy bumps or thermal bumps	H10W	In the scheme	42,452
H10W90/297	Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips	H10W	In the scheme	41,586
H10W74/114	Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations	H10W	In the scheme	41,056
H10W70/614	Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed	H10W	In the scheme	40,863
H10W46/00	Marks applied to devices, e.g. for alignment or identification	H10W	In the scheme	40,634
H10W74/10	Encapsulations, e.g. protective coatings characterised by their shape or disposition	H10W	In the scheme	40,272
H10W72/019	Manufacture or treatment of bond pads	H10W	In the scheme	40,259
H10W90/753	Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips	H10W	In the scheme	38,776
H10W74/014	Manufacture or treatment using batch processing	H10W	In the scheme	37,742
H10W44/20	Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]	H10W	In the scheme	37,725
H10W72/5449	Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements	H10W	In the scheme	37,114
H10W70/09	Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs	H10W	In the scheme	36,956
H10W90/401	Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs	H10W	In the scheme	36,784
H10W74/019	Manufacture or treatment using temporary auxiliary substrates	H10W	In the scheme	36,566
H10W72/071	Connecting or disconnecting	H10W	In the scheme	36,194
H10W72/9413	Dispositions of bond pads on encapsulations	H10W	In the scheme	36,169
H10W74/016	Manufacture or treatment using moulds	H10W	In the scheme	36,015
H10W42/20	Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons	H10W	In the scheme	35,428
H10W72/5524	Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]	H10W	In the scheme	35,119
H10W72/0711	Apparatus therefor	H10W	In the scheme	34,730
H10W70/68	Shapes or dispositions thereof	H10W	In the scheme	34,132
H10W72/877	Bump connectors and die-attach connectors	H10W	In the scheme	33,978
H10W42/121	Arrangements for protection of devices protecting against mechanical damage	H10W	In the scheme	33,823
H10W72/5445	Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements	H10W	In the scheme	32,954
H10W40/255	Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates	H10W	In the scheme	32,562
H10W72/325	Die-attach connectors having a filler embedded in a matrix	H10W	In the scheme	32,020
H10W40/47	Arrangements for thermal protection or thermal control involving heat exchange by flowing fluids by flowing liquids, e.g. forced water cooling	H10W	In the scheme	31,894
H10W72/07141	Means for applying energy, e.g. ovens or lasers	H10W	In the scheme	31,194
H10W72/926	Multiple bond pads having different sizes	H10W	In the scheme	30,968
H10W74/012	Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills	H10W	In the scheme	30,691
H10W40/10	Arrangements for heating	H10W	In the scheme	30,532
H10W72/07554	Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions	H10W	In the scheme	30,400
H10W72/874	On different surfaces	H10W	In the scheme	29,537
H10W74/129	Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]	H10W	In the scheme	29,253
H10W95/00	Packaging processes not covered by the other groups of this subclass	H10W	In the scheme	28,518
H10W72/5525	Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]	H10W	In the scheme	27,856
H10W72/07331	Connecting techniques	H10W	In the scheme	27,690
H10W70/095	Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein	H10W	In the scheme	27,186
H10W70/682	Shapes or dispositions thereof comprising holes having chips therein	H10W	In the scheme	27,020
H10W74/142	Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body	H10W	In the scheme	26,783
H10W90/811	Multiple chips on leadframes	H10W	In the scheme	26,431
H10W74/47	Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins	H10W	In the scheme	26,391
H10W72/942	Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias	H10W	In the scheme	25,957
H10W72/251	Materials	H10W	In the scheme	25,570
H10W72/244	Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias	H10W	In the scheme	25,360
H10W90/792	Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips	H10W	In the scheme	24,920
H10W42/00	Arrangements for protection of devices	H10W	In the scheme	24,665
H10W72/547	Dispositions of multiple bond wires	H10W	In the scheme	23,831
H10W72/07336	Soldering or alloying	H10W	In the scheme	23,407
H10W72/552	Materials of bond wires comprising metals or metalloids, e.g. silver	H10W	In the scheme	23,069
H10W72/944	Dispositions of multiple bond pads	H10W	In the scheme	22,675
H10W40/73	Fillings or auxiliary members in containers or in encapsulations for thermal protection or control for cooling by change of state	H10W	In the scheme	22,603
H10W70/655	Fan-out layouts	H10W	In the scheme	22,387
H10W70/481	Leadframes for devices being provided for in groups H10D8/00 - H10D48/00	H10W	In the scheme	22,028
H10W90/20	Configurations of stacked chips	H10W	In the scheme	21,480
H10W72/951	Materials of bond pads	H10W	In the scheme	21,193
H01L25/0657	Retired code	H10W	Retired, by concordance	20,905
H10W74/121	Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation	H10W	In the scheme	20,433
H10W70/69	Insulating materials thereof	H10W	In the scheme	20,395
H10W40/228	Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped	H10W	In the scheme	20,285
H10W72/242	Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding	H10W	In the scheme	20,213
H01L2924/00	Retired code	H10W	Retired, by concordance	20,139
H10W74/40	Encapsulations, e.g. protective coatings characterised by their materials	H10W	In the scheme	20,083
H10W70/421	Shapes or dispositions	H10W	In the scheme	19,768
H10W72/9445	Top-view layouts, e.g. mirror arrays	H10W	In the scheme	19,403
H10W72/934	Cross-sectional shape, i.e. in side view	H10W	In the scheme	19,065
H10W40/226	Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area	H10W	In the scheme	18,792
H10W74/137	Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body	H10W	In the scheme	18,307
H10W46/301	Marks applied to devices, e.g. for alignment or identification for alignment	H10W	In the scheme	18,127
H10W70/692	Ceramics or glasses	H10W	In the scheme	18,119
H10W76/60	Seals	H10W	In the scheme	18,090
H10W70/63	Vias, e.g. via plugs	H10W	In the scheme	17,749
H10W90/291	Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips	H10W	In the scheme	17,621
H10W72/07254	Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions	H10W	In the scheme	17,594
H10W90/752	Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips	H10W	In the scheme	17,499
H10W72/07533	Ultrasonic bonding, e.g. thermosonic bonding	H10W	In the scheme	17,452
H01L25/0753	Retired code	H10W	Retired, by concordance	17,242
H10W40/778	Auxiliary members characterised by their shape in encapsulations	H10W	In the scheme	17,183
H01L24/16	Retired code	H10W	Retired, by concordance	17,138
H10W40/43	Arrangements for thermal protection or thermal control involving heat exchange by flowing fluids by flowing gases, e.g. forced air cooling	H10W	In the scheme	16,778
H10W80/312	Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads	H10W	In the scheme	16,777
H10W80/327	Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers	H10W	In the scheme	16,581
H10W70/688	Flexible insulating substrates	H10W	In the scheme	16,509
H10W90/288	Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips	H10W	In the scheme	16,387
H10W72/5473	Dispositions of multiple bond wires multiple bond wires connected to a common bond pad	H10W	In the scheme	16,373
H10W72/01515	Forming coatings	H10W	In the scheme	16,292
H01L25/50	Retired code	H10W	Retired, by concordance	16,281
H10W40/258	Metallic materials	H10W	In the scheme	16,033
H10W90/22	Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL	H10W	In the scheme	15,841
H10W44/248	Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements for antennas	H10W	In the scheme	15,839
H10W72/07337	Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy	H10W	In the scheme	15,518
H10W72/01225	Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping	H10W	In the scheme	15,423
H10W72/247	Dispositions of multiple bumps	H10W	In the scheme	15,350
H10W72/856	Bump connectors and die-attach connectors	H10W	In the scheme	15,227
H10W72/5475	Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires	H10W	In the scheme	15,209
H10W90/24	Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape	H10W	In the scheme	15,194
H10W72/222	Multilayered bumps, e.g. a coating on top and side surfaces of a bump core	H10W	In the scheme	15,070
H10W72/013	Manufacture or treatment of die-attach connectors	H10W	In the scheme	14,929
H01L23/481	Retired code	H10W	Retired, by concordance	14,856
H10W40/25	Arrangements for cooling characterised by their materials	H10W	In the scheme	14,739
H10W72/07354	Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions	H10W	In the scheme	14,729
H10W40/251	Organics	H10W	In the scheme	14,600

Match: Direct

The capability is itself a technology or a kind of physical system, and the classification names it. Coverage is mainly CPC: the package entries H10W72 and H10W90 carry almost no IPC use, and the older H01L23 and H01L25 are absent from the scheme. The crosswalk is a first pass that nobody has reviewed.

Advanced Packaging & Heterogeneous Integration

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Global

Japan

South Korea

United States

Taiwan

China

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