Critical Technology

Semiconductor Design & EDA

The capacity to design leading-edge semiconductors and to command the design layer itself, electronic design automation, intellectual-property cores and verification, on which all design depends. One of the capabilities of Semiconductors & Advanced Computing.

International families: 9,0702015 to 2024
Leading country: United States1.2× the next
All families: 36khome filings included
Over five years: Rising2020 to 2024 against the five before

Year by year

Patent families by country of origin and the year of the earliest filing, 2000 to 2025; 2025 is a part year, still filling in. International families are those for which protection was sought beyond one country.

Volume

International patent families in the capability, by the year of the earliest filing.

Source: Global Institute for National Capability (GINC), 2026. Underlying patents from 107 patent offices, IFI CLAIMS and Google

Share by country

Each country's share of the year's international families, in per cent: the capability's five largest countries of origin, 2015 to 2024, and the rest of the world.

Source: Global Institute for National Capability (GINC), 2026. Underlying patents from 107 patent offices, IFI CLAIMS and Google

Country leaderboard

International patent families, 2015 to 2024, by country of origin. Growth compares the latest five full years with the five before.

Ten largest

United States

Taiwan

China

South Korea

Japan

Germany

United Kingdom

Netherlands

France

Israel

2,117

1,739

1,459

1,379

1,123

307

180

145

128


1	United States	2,117	23.3%	1.4×	5,913
2	Taiwan	1,739	19.2%	1.2×	2,214
3	China	1,459	16.1%	2.6×	22,131
4	South Korea	1,379	15.2%	1.7×	1,952
5	Japan	1,123	12.4%	1.0×	1,461
6	Germany	307	3.4%	1.4×	430
7	United Kingdom	180	2.0%	1.0×	271
8	Netherlands	145	1.6%	0.6×	155
9	France	128	1.4%	0.6×	149
10	Israel	53	0.6%	1.4×	96
11	Switzerland	52	0.6%	3.0×	64
12	Singapore	51	0.6%	1.8×	82
13	Belgium	49	0.5%	2.1×	55
14	Austria	42	0.5%	1.5×	45
15	Canada	39	0.4%	1.6×	75
16	Cayman Islands	32	0.4%	0.1×	163
17	Italy	24	0.3%	0.5×	29
18	India	24	0.3%	1.4×	67
19	Sweden	14	0.2%	0.8×	16
20	Finland	14	0.2%	0.8×	18
21	Ireland	10	0.1%	1.5×	14
22	Australia	9	0.1%	1.3×	10
23	Hong Kong	7	0.1%	0.2×	10
24	Malaysia	7	0.1%	6.0×	11
25	Spain	6	0.1%	1.0×	7
26	Portugal	6	0.1%	0.5×	6
27	Türkiye	5	0.1%	1.5×	7
28	Norway	5	0.1%	–	8
29	Saudi Arabia	5	0.1%	0.3×	14
30	Russia	3	0.0%	2.0×	13
31	Denmark	2	0.0%	1.0×	2
32	Brazil	2	0.0%	1.0×	6
33	Poland	2	0.0%	–	3
34	Czechia	2	0.0%	1.0×	5
35	Hungary	2	0.0%	1.0×	2
36	New Zealand	1	0.0%	0.0×	1
37	South Africa	1	0.0%	–	1
38	Mexico	0	0.0%	–	1

Applicants

The largest applicants by international patent families, 2015 to 2024: across the world, then within each of the five countries with the most families in Semiconductor Design & EDA. Names are as held in the source and are not consolidated across subsidiaries.

Global

9,070 international families

TAIWAN SEMICONDUCTOR MFG CO LTD · Taiwan

SAMSUNG ELECTRONICS CO LTD · South Korea

TAIWAN SEMICONDUCTOR MFG · Taiwan

INTEL CORP · United States

SYNOPSYS INC · United States

QUALCOMM INC · United States

1,190

1,068

520

254

191

178

United States

2,117 international families

INTEL CORP

SYNOPSYS INC

QUALCOMM INC

IBM

SIEMENS IND SOFTWARE INC

MICRON TECHNOLOGY INC

252

190

178

146

Taiwan

1,739 international families

TAIWAN SEMICONDUCTOR MFG CO LTD

TAIWAN SEMICONDUCTOR MFG

UNITED MICROELECTRONICS CORP

REALTEK SEMICONDUCTOR CORP

MEDIATEK INC

TAIWAN INTEGRATED CIRCUIT MFG SHARE LIMITED COMPANY

1,175

518

137

China

1,459 international families

CHANGXIN MEMORY TECH INC

HUAWEI TECH CO LTD

BOE TECHNOLOGY GROUP CO LTD

SEMICONDUCTOR MFG INT SHANGHAI CORP

VAYO SHANGHAI TECH CO LTD

SEMICONDUCTOR MFG INT BEIJING CORP

148

South Korea

1,379 international families

SAMSUNG ELECTRONICS CO LTD

SK HYNIX INC

SAMSUNG DISPLAY CO LTD

SAMSUNG ELECTRONIC JOINT BASED CONSULTATION

SEOUL NAT UNIV R&DB FOUNDATION

ELECTRONICS & TELECOMMUNICATIONS RES INST

1,066

Japan

Japan

United States

China

Germany

South Korea

106,439

60,107

40,792

37,205

32,878

Crosswalk

How Semiconductor Design & EDA is matched to the patent classifications. The entries below were chosen for it; each stands for itself and everything beneath it in the scheme, 98 Cooperative entries in all. A patent family counts when any of its codes, in either scheme and at any office, falls under one of them. Codes since retired are placed under the entries that replaced them.

Entry	Title in the scheme	Why it is chosen	CPC codes	IPC codes	Documents
G06F30/30	Circuit design	Circuit design automation: logic, layout, verification	28	28	213,917
G06F2115/00	Details relating to the type of the circuit	Circuit types addressed by design automation	7	none	10,135
G06F2117/00	Details relating to the type or aim of the circuit design	Aims of circuit design, e.g. low power, testability	7	none	3,676
H10D89/10	Integrated device layouts	Integrated circuit layouts	2	1	44,217
H10D84/90	Masterslice integrated circuits	Gate arrays and standard-cell integrated circuits	51	1	26,322

CPC and IPC codes are the codes in use on patent documents, at any office, that fall under the entry. Documents is the larger of the two schemes' counts of documents carrying one of them. An entry with no IPC codes can be told apart only in the Cooperative scheme.

The Cooperative codes in use that count towards Semiconductor Design & EDA: 95 codes on 298,267 documents. The full crosswalk is in the cpc-to-capability.csv download.

Code	Title	Under entry	How placed	Documents
H10D89/10	Integrated device layouts	H10D89/10	In the scheme	42,780
G06F30/398	Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]	G06F30/30	In the scheme	30,272
G06F30/392	Floor-planning or layout, e.g. partitioning or placement	G06F30/30	In the scheme	25,374
G06F30/367	Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods	G06F30/30	In the scheme	23,767
G06F30/39	Circuit design at the physical level	G06F30/30	In the scheme	18,195
G06F30/30	Circuit design	G06F30/30	In the scheme	15,797
G06F30/394	Routing	G06F30/30	In the scheme	15,149
G06F30/33	Design verification, e.g. functional simulation or model checking	G06F30/30	In the scheme	14,320
G06F30/327	Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist	G06F30/30	In the scheme	11,300
H10D84/907	CMOS gate arrays	H10D84/90	In the scheme	8,215
G06F30/34	Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]	G06F30/30	In the scheme	7,970
G06F30/3308	Design verification, e.g. functional simulation or model checking using simulation	G06F30/30	In the scheme	6,823
G06F30/3312	Timing analysis	G06F30/30	In the scheme	6,572
G06F30/3323	Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking	G06F30/30	In the scheme	5,124
G06F30/331	Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation	G06F30/30	In the scheme	4,127
G06F30/36	Circuit design at the analogue level	G06F30/30	In the scheme	3,830
G06F2115/12	Printed circuit boards [PCB] or multi-chip modules [MCM]	G06F2115/00	In the scheme	3,722
G06F30/337	Design optimisation	G06F30/30	In the scheme	3,102
G06F30/347	Physical level, e.g. placement or routing	G06F30/30	In the scheme	2,602
G06F30/373	Design optimisation	G06F30/30	In the scheme	2,573
G06F30/396	Clock trees	G06F30/30	In the scheme	2,502
G06F30/31	Design entry, e.g. editors specifically adapted for circuit design	G06F30/30	In the scheme	2,432
H10D84/90	Masterslice integrated circuits	H10D84/90	In the scheme	2,345
G06F2115/02	System on chip [SoC] design	G06F2115/00	In the scheme	2,313
G06F30/333	Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]	G06F30/30	In the scheme	2,304
H10D84/975	Wiring regions or routing	H10D84/90	In the scheme	2,175
G06F30/343	Logical level	G06F30/30	In the scheme	2,055
H10D84/903	Masterslice integrated circuits comprising field effect technology	H10D84/90	In the scheme	1,972
H10D84/998	Input and output buffer/driver structures	H10D84/90	In the scheme	1,865
G06F2115/08	Intellectual property [IP] blocks or IP cores	G06F2115/00	In the scheme	1,737
H10D84/981	Power supply lines	H10D84/90	In the scheme	1,719
G06F30/3315	Design verification, e.g. functional simulation or model checking using static timing analysis [STA]	G06F30/30	In the scheme	1,606
G06F30/32	Circuit design at the digital level	G06F30/30	In the scheme	1,444
H10D89/105	Integrated device layouts adapted for thermal considerations	H10D89/10	In the scheme	1,437
G06F2117/08	HW-SW co-design, e.g. HW-SW partitioning	G06F2117/00	In the scheme	1,333
G06F30/3953	Routing detailed	G06F30/30	In the scheme	1,241
G06F30/323	Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation	G06F30/30	In the scheme	1,196
G06F2115/06	Structured ASICs	G06F2115/00	In the scheme	1,047
G06F30/3947	Routing global	G06F30/30	In the scheme	1,043
G06F2115/10	Processors	G06F2115/00	In the scheme	1,030
H10D84/966	Gate electrode terminals or contacts	H10D84/90	In the scheme	741
G06F2117/12	Sizing, e.g. of transistors or gates	G06F2117/00	In the scheme	713
G06F2117/04	Clock gating	G06F2117/00	In the scheme	684
H10D84/974	Layout specifications, i.e. inner core regions	H10D84/90	In the scheme	660
G06F30/38	Circuit design at the mixed level of analogue and digital signals	G06F30/30	In the scheme	602
G06F30/35	Delay-insensitive circuit design, e.g. asynchronous or self-timed	G06F30/30	In the scheme	595
G06F2117/02	Fault tolerance, e.g. for transient fault suppression	G06F2117/00	In the scheme	537
H10D84/987	Three levels of metal	H10D84/90	In the scheme	525
H10D84/979	Data lines, e.g. buses	H10D84/90	In the scheme	509
H10D84/901	Masterslice integrated circuits comprising bipolar technology	H10D84/90	In the scheme	494
H10D84/961	Substrate and well contacts	H10D84/90	In the scheme	468
H10D84/953	Sub-micron technology	H10D84/90	In the scheme	376
H10D84/988	Four or more levels of metal	H10D84/90	In the scheme	362
H10D84/996	Masterslice integrated circuits using combined field effect technology and bipolar technology	H10D84/90	In the scheme	348
H10D84/912	4-T CMOS basic cells	H10D84/90	In the scheme	314
H10D84/931	FET isolation	H10D84/90	In the scheme	305
H10D84/962	Horizontal or vertical grid line density	H10D84/90	In the scheme	297
H10D84/964	Yield or reliability	H10D84/90	In the scheme	291
G06F2115/04	Micro electro-mechanical systems [MEMS]	G06F2115/00	In the scheme	268
G06F2117/06	Spare resources, e.g. for permanent fault suppression	G06F2117/00	In the scheme	250
H10D84/938	Implementation of memory functions	H10D84/90	In the scheme	242
H10D84/914	5-T CMOS basic cells	H10D84/90	In the scheme	197
H10D84/955	Twin-tub technology	H10D84/90	In the scheme	196
H10D84/985	Two levels of metal	H10D84/90	In the scheme	189
H10D84/991	Latch-up prevention	H10D84/90	In the scheme	170
H10D84/929	Isolations	H10D84/90	In the scheme	164
G06F2117/10	Buffer insertion	G06F2117/00	In the scheme	149
H10D84/968	Macro-architecture	H10D84/90	In the scheme	109
H10D84/992	Noise prevention, e.g. preventing crosstalk	H10D84/90	In the scheme	106
H10D84/959	Connectability characteristics, i.e. diffusion and polysilicon geometries	H10D84/90	In the scheme	89
H10D84/983	Levels of metallisation	H10D84/90	In the scheme	85
H10D84/937	Implementation of digital circuits	H10D84/90	In the scheme	83
H10D84/951	Technology used, i.e. design rules	H10D84/90	In the scheme	81
H10D84/916	6-T CMOS basic cells	H10D84/90	In the scheme	73
H10D84/921	8-T CMOS basic cells	H10D84/90	In the scheme	67
H10D84/957	SOS or SOI technology	H10D84/90	In the scheme	64
H10D84/925	Microarchitecture relative P to N transistor sizes for delay time adaptation	H10D84/90	In the scheme	60
H10D84/922	Microarchitecture relative P to N transistor sizes	H10D84/90	In the scheme	51
H10D84/911	Basic cell P to N transistor counts	H10D84/90	In the scheme	43
H10D84/924	Microarchitecture relative P to N transistor sizes for current drive capability	H10D84/90	In the scheme	42
H10D84/948	Transmission gates	H10D84/90	In the scheme	31
H10D84/971	Number of core or basic cells in the macro (RAM or ROM)	H10D84/90	In the scheme	31
H10D84/977	Avoiding clock-skew or clock-delays	H10D84/90	In the scheme	29
H10D84/942	Resistors and capacitors	H10D84/90	In the scheme	28
H10D84/935	Degree of specialisation for implementing specific functions	H10D84/90	In the scheme	23
H10D84/927	Microarchitecture relative P to N transistor sizes for capacitive loading	H10D84/90	In the scheme	19
G06F2115/00	Details relating to the type of the circuit	G06F2115/00	In the scheme	18
H10D84/972	Distribution functions, e.g. sea of gates	H10D84/90	In the scheme	15
H10D84/918	7-T CMOS basic cells	H10D84/90	In the scheme	12
H10D84/941	Implementation of analog circuits	H10D84/90	In the scheme	11
G06F2117/00	Details relating to the type or aim of the circuit design	G06F2117/00	In the scheme	10
H10D84/905	A3B5 or A3B6 gate arrays	H10D84/90	In the scheme	9
H10D84/909	Microarchitecture	H10D84/90	In the scheme	9
H10D84/994	Radiation hardened circuits	H10D84/90	In the scheme	8
H10D84/944	Hybrid analog or digital	H10D84/90	In the scheme	5

Match: Direct

The capability is itself a technology or a kind of physical system, and the classification names it. G06F30 dates from 2020 and the earlier G06F17/50 is absent from the scheme, so older design-automation patents are missed; H10D89/10 is thin in IPC. The crosswalk is a first pass that nobody has reviewed.

Semiconductor Design & EDA

Year by year

Volume

Share by country

Country leaderboard

Ten largest

Applicants

Global

United States

Taiwan

China

South Korea

Japan

Similar capabilities

Crosswalk

Other capabilities in Semiconductors & Advanced Computing